The present invention relates generally to electrically erasable and programmable read-only memory (EEPROM) devices and more particularly to an improved EEPROM cell and its method of use having smaller layout size, lower program/erase voltage requirements and higher read, erase and programming speeds and better endurance than conventional EEPROMS.
The semiconductor community faces increasingly difficult challenges as it moves into production of semiconductor devices at feature sizes approaching 0.1 micron. Cell designs for typical semiconductor devices must be made more durable, smaller (i.e., scalable), cost effective to manufacture, faster in reading and capable of operating at lower voltages and power to enable manufacturers to compete in the semiconductor industry.
One of the more recent generation of memories facing those challenges, EEPROMS allow their program contents to be electrically programmed bit-by-bit and electrically erased. Conventional erasable programmable read-only memories (EPROMS), by way of contrast, are generally erased in bulk and by the frequently inconvenient technique of exposure to ultraviolet light. EEPROM cells have been recently extensively used in programmable logic devices (PLD's).
Most conventional EEPROM cells are formed of three transistors: a write transistor, a read transistor and a sense transistor. The EEPROM cell is programmed and erased by removing electrons from, or adding electrons to, a floating gate of one of the transistors. In conventional EEPROM cells the read transistor and the sense transistor are connected to the same data (bitline). As a result, when the read transistor is turned on, the sense transistor is effectively used as the storage cell of the EEPROM.
FIG. 1 shows an array of four identical conventional EEPROM memory cell structures designated A, B, C and D which form a portion of a larger array composed of identical memory cell structures. The voltage lines to the other cells in the larger array not depicted in the figure have the symbol "!" as a prefix, just as is the case for cells B, C and D, unless those lines to the other cells are the same lines as are attached to cell A. The EEPROM memory cell A consists of a write transistor 12a, a read transistor 14, a sense transistor 16, a control gate capacitor C and a tunnel diode TD. Each of the three transistors has drain and source regions marked D and S, respectively. The operation of the conventional EEPROM memory cell A is summarized in Table 1 below.
TABLE 1 SUB- WBL ACG WL PT PTG WLR STRATE Program V.sub.pp 0 V.sub.pp + V.sub.t HiZ 0 V.sub.cc 0 Erase 0 V.sub.pp + V.sub.t V.sub.cc HiZ V.sub.pp V.sub.cc 0 !Program V.sub.pp 0 0 HiZ 0 0 0 (row) !Program 0 [?0][V.sub.pp + V.sub.t ?] 0 HiZ 0 0 0 (col) Read 0 0 V.sub.cc V.sub.pt 0 V.sub.cc 0
When programming the memory cell A, an intermediate pumped programming voltage V.sub.pp (typically about 11-12 V) is applied to the bitline WBL of the write transistor 12a and a relatively high voltage V.sub.pp +V.sub.t (typically between 13-15 V) is applied to its wordline WL in order to pass V.sub.pp through the tunnel diode TD to the sense transistor 16. Under this bias condition, a voltage drop is present between V.sub.d and the floating gate FG. Due to the drop, electrons tunnel from the floating gate to V.sub.d, thereby reducing or eliminating the negative charge on the floating gate of the sense transistor 16 and thus turning on the sense transistor.
When erasing the memory cell A, the relatively high voltage V.sub.pp +V.sub.t is applied to the capacitor C from array control gate line ACG. Under this bias condition, a voltage drop is present between the floating gate FG and V.sub.d. As a result, electrons tunnel from V.sub.d to floating gate FG, thereby negatively charging FG and turning off the sense transistor 16.
When reading the contents of the memory cell A, zero volts is applied to the bitline of the write transistor 12a. A voltage, V.sub.cc of about 1.8 V, is applied to the wordline WL and a voltage V.sub.pt of about 0.6-1.4 V is applied to the drain of the read transistor 14.
For each operation (read, program, erase), the substrate of the cell (not shown) is held at ground potential. The high voltage V.sub.pp +V.sub.t can be generated through an additional circuit (not shown). However, the higher the voltage V.sub.pp +V.sub.t needed, the more complex the semiconductor process and circuitry required.
While programming the memory cell A, voltages are applied to the write transistors 12b, 12c of memory cells B and C. In some cases the same voltages as are applied in cell A are applied to nodes in cells B and C corresponding to nodes in cell A because the voltage lines are shared. In other cases different voltages are applied. For example, bit line WBL applies a voltage V.sub.pp to the drain of cell B's write transistor 12b while word line !WL applies a zero voltage to the gate of that write transistor. As a result, the write transistor of memory cell B experiences a voltage of V.sub.pp over the oxide of that transistor. The large size of V.sub.pp, about 11 V, requires that that oxide be thick, about 150 .ANG., to prevent gate leakage by tunneling across the oxide which could damage the oxide. Similarly, in memory cell C, word line WL applies a high voltage of V.sub.pp +V.sub.t to the gate of that cell's write transistor 12c while bit line !WBL applies a voltage of zero to the drain of that write transistor, producing a voltage of V.sub.pp +V.sub.t across the oxide of that write transistor. As was true of the write transistor 12b in cell B, the large size of V.sub.pp +V.sub.t, about 12-14 V, also requires that the oxide of the write transistor 12c in cell C be thick. A thick oxide, as is well known in the art, renders difficult the scaling down of the transistor of which it is a component, in this case the write transistor.
The non-scalability of the write transistors prevents the scaling down of the entire EEPROM memory cell. The inability to scale down the memory cell size is undesirable because the trend in the electronics industry is to have smaller and smaller memory cells to enable an array of the same physical size to store larger and larger amounts of data.
Another drawback associated with the conventional EEPROM structure is that the thick oxide slows down the speed with which the EEPROM cell can be programmed, erased and read. This problem conflicts with the industry trend of manufacturing faster PLDs.
Thus, there is a need to provide an EEPROM memory cell structure and operating method which provide scalability and faster operating speeds while at the same time using smaller program/erase voltages, thereby increasing the endurance of the EEPROM memory cell.